This relates generally to integrated circuits, and more particularly, to integrated circuits with wireless communications circuitry.
Wireless integrated circuits such as transceiver circuits are sometimes configured to support complex, non-constant envelope modulation schemes such as the Wideband Code Division Multiple Access (W-CDMA) modulation scheme and the Orthogonal Frequency-Division Multiplexing (OFDM) modulation scheme. High frequency signals generated using such types of radio access technologies can exhibit high peak-to-average ratios (PARs), which can adversely impact the efficiency of radio-frequency power amplifiers used in wireless base transceiver stations (as an example). Reducing the PAR of these signals can help increase power amplifier efficiency and allows for higher average power to be transmitted.
In an effort to reduce signal PAR, a crest factor reduction (CFR) algorithm has been developed that involves iteratively cancelling unwanted signal peaks using a set of kernel impulses. A typical CFR processor includes a peak detection unit and multiple pulse memory blocks. When the CFR processor receives an input waveform, the peak detection unit is used to determine where the input waveform exceeds a predetermined peak magnitude threshold. The peak detection unit then directs the pulse memory blocks to output corresponding kernel impulses. Each kernel impulse is aligned (i.e., magnitude and phase are adjusted) to a corresponding peak in the input waveform. The different kernel impulses are summed to create a cancellation waveform. The summed cancellation waveform is subtracted from a delayed version of the input waveform to produce an output waveform with reduced PAR.
In the convention CFR processor, each pulse memory block stores an identical copy of an entire kernel impulse signal. In order to concurrently cancel a large number (for example 10) of unwanted signal peaks using the conventional CFR processor, an acceptably large number of pulse memory blocks may be required.